资源列表
CSOMP
- 压缩感知稀疏信号的重构代码，用到OMP算法实现过程-Compressed sensing reconstruction of sparse signal code, used in the process of OMP algorithm
DC_Motor_Main
- 基于FPGA的verilog语言，实现对直流电机的PWM控制，包括电路图、主程序、控制模块、测速模块等-Based on FPGAVeriloglanguage, realization of PWM control of DC motors, including circuit diagrams, master, control module, the speed module
DIGITLOCK
- 该程序使用VHDL在BASYS2板上实现了数字密码锁的设计，平台为Xilinx12-The program uses VHDL realization of the digital board in BASYS2 lock design platform for Xilinx12
FPGADE270CACULATOR
- 本文介绍了一个简单的计算器的设计，该设计采用了现场可编程逻辑器件FPGA设计，并基于VHDL语言实现加减乘除功能，并用十进制显示在LCD1602上。-This article describes a simple calculator design that uses a field programmable logic device FPGA design and VHDL language based on arithmetic functions, and decimal display
DSB
- FPGA中实现的DSB的AM调制，带Modelsim仿真，实际测试通过：载波频率，信号频率以及调制度可调。-The FPGA implemented in the DSB AM modulation with Modelsim simulation, the actual test: the carrier frequency, and modulation signal frequency is adjustable.
FSK
- FPGA实现FSK调制，带Modelsim仿真，实际系统测试通过，载波信号，信号频率等可调。-FPGA implementation FSK modulation with Modelsim simulation, the actual system test, the carrier signal, the signal frequency is adjustable.
MIPS_32numbers_32bits
- MIPS架构下的32位32个寄存器组的verilog源码-MIPS architecture 32 32 register banks verilog source
dds(9854)_test(sin_cos)(EP1C6)
- 通过FPGA控制DDS(AD9854)输出120M一下的双路正交信号，实现在通信和控制领域的应用。-Controlled by FPGA DDS (AD9854) output 120 m the dual orthogonal signal, realize the application in the field of communication and control.
jiajian
- 利用Verilog语言编写的按键实现数码管显示数字的加减，通过三个按键分别实现加1和减1操作 以及复位操作，BASYS2开发板验证。-Verilog language use buttons to achieve digital display digital subtraction achieve plus one and minus one operation and reset operation, BASYS2 development board were verified by thr
SDRAM-verilog
- SDRAM控制器.用verilog实现SDRAM的读写操作。-sdram coll
simple-pipeLine-CPU
- 简单的流水线CPU实现，基于MIPS指令集。-Simple pipelined CPU implementation, based on the MIPS instruction set.
t_sensor
- 数字温度计的Verilog实现，有时钟控制模块，显示模块，温度计控制模块。-digital temperature sensor