资源列表
Nios_SDRAM
- 在Nios上搭建平台，使用SDRAM作内存，并用VGA显示图像-A platform on the Nios SDRAM for memory, and VGA display image
Basic_Nios
- This starter kit is for developing embedded system in FPGAs using NIOS.
sdh_doc
- 韦乐平老师的全本《光同步数字传输网》，PDF格式，很清晰。-Wei Leping all the teachers, " Synchronous Digital Transmission Network" , PDF format, is very clear.
singnalandsystem(zhengjunli)
- 信号与系统（郑君里第二版） 傅式变换，拉式变化，FFT-signal and system
dvi_output
- DVI output modelsim simulation
reload_fir
- 这是我在Xilinx公司的FPGA上实现的FIR滤波器，调用的内部核，其特色是可以用较少的资源实现该功能，而且可以实现参数重载，即从外部MCU设置FIR滤波器的参数-This is my Xilinx FPGA to achieve the FIR filter, called internal audit, its characteristics can be achieved with fewer resources to this function, and the overload p
IIR-FPGA
- 基于FPGA实现IIR滤波器的程序，用VERILOG编程语言实现-The program based on the FPGA implementation of the IIR filter is implemented in the VERILOG programming language
Timing-analysis
- FPGA玩转Altera之时序篇，包括时序分析注意事项-Altera play the FPGA XuPian, including timing analysis the matters needing attention
Verilog_HDL_v2
- Verilog_HDL_那些事儿_时序篇v2,找了好久才找到的电子书。-Verilog_HDL_ those things _ timing V2, for a long time to find books.
Experiment
- 黑金开发板历程代码第一部分,关于时序的一部分代码-verilog for the HeiJin FPGA
DDS
- DDS数字频率合成的verilog代码，附有正余弦查找表等-DDS digital frequency synthesis verilog code, with a cosine look-up table, etc.
EP1C3
- 这是一个用Verilog语言编写的一组程序，主要是熟悉开发板的应用，以及verilog语言-This is a Verilog language with a set of procedures, mainly familiar with the application development board, and the verilog language