资源列表
FPGA-Prototyping-by-VHDL-Examples---Xilinx-Sparta
- FPGA prototyping by VHDL examples include FIFO,RAM,ROM,filters, registers and others-FPGA prototyping by VHDL examples include FIFO,RAM,ROM,filters, registers and others
fpgahdl_xilinx-edk.tar
- xilinx zynq 7000 FPGA demo-xilinx zynq 7000 FPGA demo
DE0_development_board_cd_data
- 这是DE0开发板的光盘资料，是友晶公司的关于altera公司的Cyclone III开发板。-This is DE0 development board disc material, is friend chip of altera company Cyclone III development board.
FPGA
- fpga实现图像的变换，图像旋转放大-fpga implementation image transform, image rotation and magnification
Nios_SDRAM
- 在Nios上搭建平台，使用SDRAM作内存，并用VGA显示图像-A platform on the Nios SDRAM for memory, and VGA display image
Basic_Nios
- This starter kit is for developing embedded system in FPGAs using NIOS.
sdh_doc
- 韦乐平老师的全本《光同步数字传输网》，PDF格式，很清晰。-Wei Leping all the teachers, " Synchronous Digital Transmission Network" , PDF format, is very clear.
singnalandsystem(zhengjunli)
- 信号与系统（郑君里第二版） 傅式变换，拉式变化，FFT-signal and system
dvi_output
- DVI output modelsim simulation
reload_fir
- 这是我在Xilinx公司的FPGA上实现的FIR滤波器，调用的内部核，其特色是可以用较少的资源实现该功能，而且可以实现参数重载，即从外部MCU设置FIR滤波器的参数-This is my Xilinx FPGA to achieve the FIR filter, called internal audit, its characteristics can be achieved with fewer resources to this function, and the overload p
IIR-FPGA
- 基于FPGA实现IIR滤波器的程序，用VERILOG编程语言实现-The program based on the FPGA implementation of the IIR filter is implemented in the VERILOG programming language
Timing-analysis
- FPGA玩转Altera之时序篇，包括时序分析注意事项-Altera play the FPGA XuPian, including timing analysis the matters needing attention