资源列表
Verilog_HDL_v2
- Verilog_HDL_那些事儿_时序篇v2,找了好久才找到的电子书。-Verilog_HDL_ those things _ timing V2, for a long time to find books.
Experiment
- 黑金开发板历程代码第一部分,关于时序的一部分代码-verilog for the HeiJin FPGA
DDS
- DDS数字频率合成的verilog代码，附有正余弦查找表等-DDS digital frequency synthesis verilog code, with a cosine look-up table, etc.
EP1C3
- 这是一个用Verilog语言编写的一组程序，主要是熟悉开发板的应用，以及verilog语言-This is a Verilog language with a set of procedures, mainly familiar with the application development board, and the verilog language
verilog_dds
- verilog实现dds，用于FPGA产生正弦波，适用于Cyclone 2系列-verilog achieve dds, FPGA is used to generate the sine wave, in the Cyclone Series
Pmod-CAM-5M
- zedboard平台，OV5640自动对焦模组图像采集和显示，IIC寄存器通过软件配置-zedboard platform, OV5640 autofocus image acquisition and display module, IIC registers configured through software
Aoscilloscopebasedonmsp430andFPGA
- 一款基于msp430fg4618单片机及ep1c6q340c8 fpga的简易示波器实现方案-A msp430fg4618 Microcontroller and ep1c6q340c8 fpga based on the simple realization of the program oscilloscope
DE2_NIOS_II_IRQ_BUTTON_2012
- 基于按键中断控制NCO核的输出频率，在quartus II中仿真通过-Based on the key interrupt control the output frequency of the NCO core, through simulation in quartus II
实验二 DDS实验
- FPGA 实验程序 DDS 实验程序(FPGA PROCEDURE SHANDONG UNIVERSITY)
FPGA-Prototyping-by-VHDL-Example
- FPGA Prototyping by VHDL Example
project_PmodMic_PmodAMP2_1
- 用digilent公司的basys3开发板，外接Pmodmic和PmodAMP2模块，实现对声音的采集和复原。程序基于VIVADO 2015.4，附带例化的低通滤波器。实际可用。(Use digisen's basys3 development board, external Pmodmic and PmodAMP2 modules to achieve sound collection and recovery. The program is based on VIVADO 2015.4 wi
Verilog
- Verilog代码的基础例程，对初学FPGA来说很有帮助-Verilog code routines, helpful for the beginner FPGA