资源列表
RS232
- It s combination logic for UART. edited in verilog-HDL
vhdl
- 用状态机检测1001序列的vhdl代码 1001 sequence detection using the state machine vhdl code-1001 sequence detection using the state machine vhdl code
miaobiao
- 是电子手表的程序，基本上和市面上的电子表显示方式一样，XX：XX的格式-Procedures for electronic watches, and the market is basically the same manner as the electronic table shows, XX: XX format
clock_divider
- This code contains the simple program that can be used for the clock divider to set any desireable clock from the master clock.
LEDDecoding
- 一种简单的LED译码程序，为初学者提供现成的LED编写程序。-a kind of LED program 。
Downloads
- clock divider in verilog for FPGA use
dds_vhdl
- DDS程序 程序包含端口说明 模块设定 以及随机存储器的设计-DDS Program Program Descr iption module containing the port settings and random access memory design
cpld
- 通过单片来控制CPLD，从而达到 扩增引脚功能-Through the single chip to control CPLD, so as to achieve the amplification pins function
pit8253
- this is a code of 8253 programme interval timer in verilog
divider
- 分频器，可以实现简单的分频功能,适合初学VHDL语言的初学者-divider , it can realize simple divier
keyboard
- vhdl简单的键盘程序，可以通过它来初步的了解vhdl键盘程序的相关编写，具体功能是按键并显示相关的代码-vhdl simple keyboard program written in it to a preliminary understanding of vhdl keyboard program, the specific function keys and display the code
pwm
- 可以利用这个程序 fpga 产生 pwm 波形-Fpga generate pwm waveform